1. Field of the Invention
This invention relates to a semiconductor device.
2. Description of the Related Art
Traditionally, it is known that an insulated gate field effect transistor (metal oxide semiconductor field effect transistor (MOSFET)) is able to realize two operation modes that are an enhancement-type (normally-off type), which is the off-state when a gate voltage is zero volt, and a depletion-type (normally-on type), which is the on-state when the gate voltage is zero volt, depending upon design requirement. In the following, conventional MOSFET structures for both the enhancement-type and the depletion-type will be described.
Initially, on the conventional enhancement-type MOSFET structure, a lateral enhancement-type n-channel MOSFET having middle voltage (for example, approximately 80V) will be described. FIG. 16 is a sectional view illustrating a structure of the conventional enhancement-type MOSFET. In the enhancement-type MOSFET (hereinafter, described as a first conventional example) shown in FIG. 16, a p-type well region 102 is disposed selectively on a surface layer of an n-type semiconductor substrate 101. Each of an n+-type source region 103, a p+-type contact region 104, and an n+-type drain region 105 is disposed selectively inside the p-type well region 102.
Further, inside the p-type well region 102, an n-type offset-diffusion-region 106 is disposed so as to cover the whole surface of an n+-type drain region 105 at the lower side thereof (the inner side of the substrate). An insulation layer 107 composed of an oxide film (SiO2) is disposed at a part sandwiched between the n+-type drain region 105 and the p-type well region 102 on the surface of the n-type offset-diffusion-region 106. A gate electrode 109 is disposed through a gate dielectric film 108 at the part sandwiched between the n+-type source region 103 and the n-type offset-diffusion-region 106 on the surface of the p-type well region 102.
An end portion of the gate electrode 109 extends on the insulation layer 107 at the n+-type drain region 105 side. The n+-type drain region 105 is separated from the gate electrode 109 by the insulation layer 107, and then the distance is enlarged between the n+-type drain region 105 and the gate electrode 109. Then an offset gate structure is configured so that the position of the gate electrode 109 is biased toward the n+-type source region 103. Then the use of the offset gate structure prevents electric field from concentrating at an end portion, which is located at the n+-type drain region 105 side, of the gate electrode 109.
On the other hand, the depletion-type MOSFET, which is the on-state when the gate voltage is zero volt as described above, can apply almost constant drain current (saturation current) between drain and source even when the gate voltage is zero volt. Then it is useful for simplifying circuit configuration such that the depletion-type MOSFET by itself can configure a reference constant current source employed for integrated circuit (IC). Moreover, the depletion-type MOSFET with middle voltage can be employed for an IC having high power supply voltage, providing a lot of flexibility in circuit design.
A conventional depletion-type MOSFET structure will be described, for example, using a lateral depletion-type n-channel MOSFET with middle voltage. FIG. 17 is a sectional view illustrating a structure of the conventional depletion-type MOSFET. On the depletion-type MOSFET shown in FIG. 17 (hereinafter, described as a second conventional example), the n-type offset-diffusion-region (corresponding to a reference numeral 116 in FIG. 17) extends over almost the whole active region, forming a structure so that the n-type drain region 105 is in contact with the n+-type source region 103 through the n-type offset-diffusion-region 116. This results in configuration of the depletion-type (see, for example, Japanese Non-patent Literature 1: S. Kiuchi et al., “Automotive Smart MOSFETs”, Fuji Jihou vol. 76 No. 10, (2003) pp. 606-611). The active region is the area where a current runs during the on-state.
Furthermore, another instance of the conventional depletion-type MOSFET structure will be described. FIGS. 18 and 19 are sectional views illustrating structures of another instances of the conventional depletion-type MOSFET. The depletion-type MOSFET shown in FIG. 18 (hereinafter, described as a third conventional example) is different from the second conventional example in that a local oxidation of silicon (LOCOS) film 117 formed by such a method for performing LOCOS is, instead of the insulation layer 107, applied to separate the n+-type drain region 105 from the gate electrode 109 in order to promote size reduction.
The depletion-type MOSFET shown in FIG. 19 (hereinafter, described as a fourth conventional example) is different from the second conventional example in that an n-type diffusion region 136 is, instead of extending the n-type offset-diffusion-region 116 over the whole active region, disposed at the part sandwiched between the n+-type source region 103 and the n-type offset-diffusion-region 106 in the p-type well region 102. It is possible to optimize n-type impurity concentration at the part beneath the gate electrode 109 (the part opposite to the gate electrode 109 through the gate dielectric film 108) in the active region. Then current characteristics can be improved (see, for example, Non-patent Literature 2: Y. Toyoda et al., “60V-Class Power IC Technology for an Intelligent Power Switch with an Integrated Trench MOSFET”, Proceedings of the 25th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2013 May, pp. 147-150).
However, according to the second to the fourth conventional examples described above, when the depletion-type MOSFET is applied to the reference constant current source in IC, there is a case that a design change is necessary to modify saturation current (current capacity) in order to tune IC characteristics. Next problems will occur. According to the second conventional example, when impurity concentration of the n-type offset-diffusion-region 116 is changed to adjust the saturation current, the impurity concentration come into the optimum value at the part beneath the gate electrode 109 (the part opposite to the gate electrode 109 through the gate dielectric film 108) in the n-type offset-diffusion-region 116. However, the impurity concentration shifts from the optimum around the n+-type drain region 105 in the n-type offset-diffusion-region 116. Then breakdown voltage characteristics cannot be maintained. That is, there is low flexibility in adjusting the impurity concentration of the n-type offset-diffusion-region 106 in order to maintain the breakdown voltage characteristics and to ensure sufficient saturation current.
According to the third conventional example described above, when impurity concentration of the n-type offset-diffusion-region 126 is changed to adjust the saturation current, the breakdown voltage characteristics cannot be maintained as similar to the second conventional example described above. That is, there is low flexibility in adjusting the impurity concentration of the n-type offset-diffusion-region 126 also on the above third conventional example. Further, according to the third conventional example described above, a p-type impurity is taken up from a silicon portion into the LOCOS film 117 by thermal oxidation process for forming the LOCOS film 117. Then the p-type impurity becomes low in concentration at the silicon portion around the interface of the LOCOS film 117. On the other hand, an n-type impurity piled up is redistributed, and the n-type impurity becomes high in concentration at the silicon portion around the interface of the LOCOS film 117. Then, the net impurity concentration of the n-type offset-diffusion-region 126 becomes high at the part beneath the LOCOS film 117 (the part opposite to the LOCOS film 117). In consideration of phenomena described above, it is possible to maintain the breakdown voltage characteristics by optimizing the impurity concentration of the n-type offset-diffusion-region 126. However, in this case, the impurity concentration becomes low at the part beneath the gate electrode 109 in the n-type offset-diffusion-region 126. Then the diffusion depth in the part becomes shallower than that in the other part. Thus sufficient saturation current cannot be ensured.
According to the fourth conventional example described above, it is possible to optimize the n-type impurity concentration of the silicon portions at the parts beneath the LOCOS film 117 and the gate electrode 109 with the aid of the n-type offset-diffusion-region 106 and an n-type diffusion region 136, respectively. Then sufficient saturation current can be ensured. However, the n-type impurity concentration increases at a part 136a where the n-type offset-diffusion-region 106 overlaps the n-type diffusion region 136. Then this might decrease breakdown voltage. Therefore, the upper-limit value is restricted in the range of the impurity concentration for the n-type diffusion region 136.